The invention pertains to semiconductor processing methods which can be utilized for forming semiconductor constructions. In particular applications, the invention encompasses methods of forming anti-fuse constructions while forming conductive interconnects. The invention also pertains to semiconductor assemblies.
It is a continuing goal of semiconductor processing to reduce the number of fabrication steps utilized in forming semiconductor devices. One method by which the number of fabrication steps can be reduced is to utilize common fabrication steps in forming two or more separate devices. The present invention encompasses new methods of utilizing common processing steps to simultaneously form portions of two or more different semiconductor structures.
In one aspect, the invention encompasses a semiconductor processing method wherein an insulative mass is formed across a first electrical node and a second electrical node. The mass has a pair of openings extending therethrough to the electrical nodes. The individual openings each have a periphery defined by one of the electrical nodes and at least one sidewall. One of the openings extends to the first electrical node and is a first opening, and the other of the openings extends to the second electrical node and is a second opening. A dielectric material layer is formed within the openings to narrow the openings. Conductive material plugs are formed within the narrowed openings. The conductive material plug within the first opening is a first material plug, and is separated from the first electrical node by the dielectric material; and the conductive plug within the second opening is a second material plug, and is not separated from the second electrical node by the dielectric material.
In another aspect, the invention encompasses a semiconductor assembly comprising an anti-fuse construction and an electrically conductive interconnect construction.